Dynamic semiconductor memory having local read amplifier driver circuits which are optimized with respect to their drive function

ABSTRACT

The dynamic semiconductor memory which has at least one block of memory (WLB), in which s block of memory has in each case a plurality of bit line blocks (TB, TB&#39; . . . ) which has for each bit line block a local SAN driver (LTN), and possibly also a local SAP driver (LTP) for driving the read amplifiers (LV) belonging to this bit line block (TB), in order to avoid interfering voltage drops on long driver lines, and which has, to achieve an optimized drive function, multi-stage local SAN drivers (LTN) or SAP drivers (LTP) whose transistors generally have different channel widths.

BACKGROUND OF THE INVENTION

The invention relates to a dynamic semiconductor memory.

A dynamic semiconductor memory of this type is known from thepublication entitled "An Experimental 16 Megabit DRAM with ReducedPeak-Current Noise" by B. Chin (Samsung) from the Digest of TechnicalPapers from the 1989 Symposium on VLSI Circuits (pages 113 and 114).This relates to a dynamic semiconductor memory having lines which areinterconnected in a block manner to metal conductors lying above ( metalstrapping ) in order to reduce the line resistance, and which hasdistributed SAN and SAP drivers, consisting of a transistor, in eachcase one SAN driver transistor and one SAP driver transistor beingpresent for each read amplifier. Since two additional transistors arethus required for each read amplifier, this entails a relatively highadditional space requirement.

SUMMARY OF THE INVENTION

The object of the invention is to disclose a dynamic semiconductormemory of the type mentioned at the beginning which permits an optimumcombination of evaluation reliability and short access time with aminimum chip space requirement. This object is achieved according to theinvention by a dynamic semiconductor memory having a memory cellarrangement which has at least one word line block. Read amplifiers havein each case an n-channel part and a p-channel part. At least one SANdriver per word line block drives the n-channel parts of the readamplifiers and at least one SAP driver per word line block drives thep-channel parts of the read amplifiers. At least one word line block hasa multiplicity of bit line blocks. The bit line blocks in turn have amultiplicity of bit line pairs, wherein, to the extent that word linesare made contact with through the board, the word lines havingsuperimposed conductor tracks which are of low impedance relative to theword lines and which have word line pins, the bit line pairs located ineach case between two word line pins of a word line form a bit lineblock. To the extent that word lines are guided only in a plane oflow-impedance material and additional word line drives are provided, thebit line pairs located in each case between two word line drivers of aword line form a bit line block. Wherein a single SAN driver is presentfor each bit line block, forms a local SAN driver and can be driven suchthat the voltage at its output decreases in a piecemeal manner, withdifferent gradients, to enable a fast and at the same time reliablereading. Wherein in each case one local SAN driver drives the n-channelparts of all read amplifiers belonging to a bit line block via a localSAN line.

The particular advantage conferred by the invention is that, with thedynamic semiconductor memory designed according to the invention, incomparison with the cited dynamic semiconductor memory from Samsung, noadditional space is required by virtue of an n-phase driver which isrequired only on a block basis with optimized drive function and, forexample, the utilization of a gap between read amplifier blocks alreadyformed by through-plated line interconnects.

Further developments of the present invention are as follows.

The local SAN driver belonging to a bit line block is arranged spatiallyon a semiconductor chip in such a way that it is located between anarrangement of read amplifiers belonging to the bit line block and anarrangement of read amplifiers which belong to the bit line blockdirectly adjacent to the bit line block.

In each case one local SAN driver contains a diode, which is connectedto a reference potential on the cathode side and is connected to a firstterminal of a first n-channel transistor on the anode side. A secondterminal of the first n-channel transistor is connected to a driveroutput of the local SAN driver and the gate terminal of the firstn-channel transistor can be driven by a first control signal. A secondn-channel transistor is connected in parallel with the diode and itsgate can be driven by a second control signal. A first terminal of athird n-channel transistor is connected to the driver output of thelocal SAN driver, and a second terminal of the third n-channeltransistor is connected to the reference potential, and the gateterminal of the third n-channel transistor can be driven by a thirdcontrol signal. At least one further n-channel transistor is connectedin parallel with the third n-channel transistor. In each case a firstterminal of the further n-channel transistor is connected to the driveroutput of the local SAN driver, and a second terminal of the furthern-channel transistor is connected to the reference potential. It ispossible for the gate terminal of the further n-channel transistor to bedriven by a further control signal. The n-channel transistor of thelocal SAN drivers can have different channel widths.

In addition to a local SAN driver, a single SAP driver with optimizeddrive function is present for each bit line block and forms a local SAPdriver. In each case one local SAP driver drives the p-channel parts ofall read amplifiers belonging to a bit line block via a local SAP line.The local SAP driver belonging to a bit line block is arranged spatiallyon a semiconductor chip in such a way that it is located between anarrangement of read amplifiers belonging to the bit line block and anarrangement of read amplifiers which belong to the bit line blockdirectly adjacent to the bit line block.

In each case one local SAP driver contains a diode, which is connectedto a supply voltage on the anode side and is connected to a firstterminal of a first p-channel transistor on the cathode side. A secondterminal of the first p-channel transistor is connected to a driveroutput of the local SAP driver and the gate terminal of the firstp-channel transistor can be driven by a first control signal. A secondp-channel transistor is connected in parallel with the diode and itsgate terminal can be driven by a second control signal. A first terminalof a third p-channel transistor is connected to the driver output of thelocal SAP driver, and a second terminal of the third p-channeltransistor is connected to the supply voltage, and the gate terminal ofthe third p-channel transistor can be driven by a third control signal.At least one further p-channel transistor is connected in parallel withthe third p-channel transistor. In each case a first terminal of thefurther p-channel transistor is connected to the driver output of thelocal SAP driver, and a second terminal of the further p-channeltransistor is connected to the supply voltage. It is possible for thegate terminal of the further p-channel transistor to be driven by afurther control signal. The p-channel transistors of the local SAPdrivers can have different channel widths.

BRIEF DESCRIPTION OF THE DRAWINGS

The features of the present invention which are believed to be novel,are set forth with particularity in the appended claims. The invention,together with further objects and advantages, may best be understood byreference to the following description taken in conjunction with theaccompanying drawings in the several Figures of which like referencenumerals identify like elements, and in which:

The invention is explained below in greater detail with reference to thedrawing, in which:

FIG. 1 shows a voltage-time diagram and a basic circuit for explainingthe effect of driver line resistances, particularly with global drivers,

FIG. 2 shows a detailed circuit of a read amplifier with coupled memorycell and bit line equivalent circuit,

FIG. 3 shows a representation of the arrangement in blocks of local SANdrivers in a dynamic semiconductor memory according to the invention,

FIG. 4 shows a detailed circuit of an n-phase local SAN driver of adynamic semiconductor memory according to the invention,

FIG. 5 shows a voltage-time diagram for explaining the n-phase local SANdriver of FIG. 4,

FIG. 6 shows a representation for the arrangement in blocks of local SANand SAP drivers in a dynamic semiconductor memory according to theinvention, and

FIG. 7 shows a detailed circuit of an n-phase Local SAP driver in adynamic semiconductor memory according to the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 1 is a voltage-time diagram which shows the voltages U_(1a) andU_(1a), of a global SAP line 1a, 1a' and the voltages U_(2a), U_(2a), ofa global SAN line 2a 2a'. In this a read amplifier LV consisting of ann-channel part SAN and a p-channel part SAP is located in the immediatevicinity of the p-channel driver transistor T₁ and of the n-channeltransistor T₂. The SAP line section 1a next to the driver connects thesource terminal of the transistor T₁ to the p-channel part SAP of theread amplifier LV, and the SAN line section 2a next to the driverconnects the drain terminal of the driver transistor T₂ to the n-channelpart SAN of the read amplifier LV. A read amplifier LV' remote from thedriver consists of an n-channel part SAN' and of a p-channel part SAP',the n-channel part SAN' being connected to an SNN line section 2a'remote from the driver and the p-channel part SAP' being connected to anSAP line section 1a' remote from the driver. A line resistor R₁ islocated between the SAP line sections next to the driver and remote fromthe driver, and a line resistor R₂ is located between the SAN linesections next to the driver and remote from the driver. The voltageU_(1a) occurring on the SAP line section next to the driver and thevoltage U_(2a) occurring on the SAN line section 2a next to the driveris represented by a broken line in the voltage-time diagram, and avoltage occurring on the SAP line section 1a' remote from the driver anda voltage U_(2a') occurring on the SAN line section 2a' remote from thedriver are represented by a solid line. The drain terminal of thep-channel driver transistor T₁ is connected to the supply voltage VDD,and the source terminal of the n-channel driver transistor T₂ isconnected to reference potential V_(SS), and the wiring of the gateterminals of both transistors is not illustrated in more detail. As timeprogresses, the voltage values U_(1a) and U_(1a') of the SAP line movefrom a precharge level U_(m) in the direction of the supply voltage VDDand during this time the voltages U_(2a) and U_(2a!) move from theprecharge voltage level U_(m) in the direction of the referencepotential V_(SS), this occurring in each case more quickly in the readamplifier LV next to the driver than in the read amplifier LV' remotefrom the driver. The different voltage curves of the voltages U_(1a) andU_(1a') and the voltage curves of U_(2a) and U_(2a') are caused by acurrent-dependent negative voltage feedback, as a result of the voltagedrop across the resistor R₁ and across the resistor R₂.

As the length of a SAP or SAN line increases, the electrical resistanceR₁ and R₂ increases and, as a result of the concomitant voltage drop,reduces the control voltage present at the read amplifier LV'. A greatdisadvantage here is that read amplifiers remote from the driver aredriven more poorly than read amplifiers next to the driver, and henceevaluate more slowly and are more susceptible to external interferinginfluences. Furthermore, no identical, optimized drive function can bespecified for all read amplifiers, since the electrical resistancebetween driver and read amplifier is different and is not negligible inrelation to the internal resistance of the driver. If, on the otherhand, the driver transistors T₁ and T₂ are driven so strongly that aread amplifier remote from the driver is sufficiently driven, then thereis the danger of incorrect evaluation at the read amplifiers next to thedriver as a result of the over-strong driving. In an extreme case, theread amplifier furthest away from the driver is to evaluate a logicalzero and the other read amplifiers are to evaluate a logical one in eachcase. In this case, the read amplifiers which are to evaluate a logicalone are activated before the read amplifier which is to evaluate alogical zero, as a result of which, for example, a discharge currentflows via the SAN line and the driver transistor T₂ to the referencepotential Vss and produces a voltage drop on the SAN line. The readamplifier which is to evaluate the logical zero will only commence theevaluation when the control voltage U=U_(m) -U_(T) (U_(m) = prechargevoltage and U_(T) =threshold voltage) is reached. If, for example, thecurrent-dependent negative voltage feedback is high as a result of theresistance R₂ of the SAN line 2a, 2a', then it may take a relativelylong time before this control voltage level is reached.

FIG. 2 shows a possible detailed circuit of a read amplifier which iscoupled to a memory cell Z via a bit line BL and which is connected to acomplementary bit line BLN. The memory cell Z consists of an n-channelMOS transistor 3, the source terminal of which is connected via a cellcapacitor 4 to reference potential, the drain terminal of which isconnected to the bit line BL, and the gate of which is connected to theword line WL. The bit line BL is represented by a Pi equivalent circuitcomprising two parallel capacitors 5 and 7 and a series resistor 6. Thecomplementary bit line BLN is represented in an analogous manner by twoparallel capacitors 8 and 10 and a series resistor 9. The bit line BLand the complementary bit line BLN are connected to the p-channel partSAP of a read amplifier consisting of two cross-coupled coupledp-channel transistors T₃ and T₄, the drain terminal of the transistor T₃and the gate terminal of the transistor T₄ being connected to the bitline BL, the drain terminal of the transistor T₄ and the gate terminalof the transistor T₃ being connected to the complementary bit line BLN,and the source terminal of the transistor T₃ being connected togetherwith the source terminal of the transistor T₄ to an SAP input E1. Thebit line BL can be short-circuited with the complementary bit line BLNby means of a transistor 12, the bit line can be precharged to a voltagepresent at the input 18 by the transistor 11, and the complementary bitline BLN can be charged to a precharge voltage present at the input 19by the transistor 13. The gates of the transistors 11 to 13 can bedriven jointly via an input 20. Two transfer transistors 14 and 15connect the bit line pair BL and BLN of the p-channel part SAP to bitline sections 22 and 23 of the n-channel part SAN of the read amplifier,and the gates of the transistors 14 and 15 can be jointly driven via aninput 21. The n-channel part SAN of the read amplifier has twocross-coupled n-channel transistors T₅ and T₆, the bit line section 22connected to the transistor 14 being connected to the drain terminal ofthe transistor T₅ and to the gate of the transistor T₆, the bit linesection 23 connected to the transfer transistor 15 being connected tothe drain of the transistor T₆ and to the gate of the transistor T₅, andthe source terminals of transistors T₅ and T₆ being connected to an SANinput E2. The bit line section 22 has a capacitor 16 and the bit linesection 23 has a capacitor 17 with respect to reference potential.

Despite a memory cell Z at a high potential, the bit line BL, togetherwith the bit line section 22, can be discharged more quickly as a resultof component dissymmetries than the complementary bit line BLN togetherwith the associated complementary bit line section 23. If, for example,the capacitance formed by the capacitors 7 and 16 is less than thecapacitance formed by the capacitors 10 and 17, or if the current gainof the transistor T₄ or that of the transistor T₅ is greater than thegain of the transistor T₃ or of the transistor T₅, then the bit line BLtogether with the bit line section 22 can erroneously be discharged morequickly than the complementary bit liner BLN with the associated bitline section 23, because as too quick a rise of the voltage from SAPinput E1 or too quick a drop of the voltage at the SAN input E2 occurs.This gives rise to the requirement for an optimized drive function forthe inputs E1 and E2. A voltage driving of the SAP input E1 and of theSAN input E2 is required in order that the optimized drive function islargely the same for all read amplifiers. A voltage control can beachieved approximately with local SAN drivers and SAP drivers.

FIG. 3 shows an arrangement in blocks of local SAN drivers LTN, LTN' . .. , in each case between read amplifiers LVB, LVB', LVB'' . . . in adynamic semiconductor memory according to the invention. A readamplifier block LVB consists of a plurality of read amplifiers, whichare connected, for example, like a read amplifier LV to a bit line pairBL and BLN and can be driven in each case via an SAN input E2. In thiscase, the SAN inputs E2 of the read amplifiers belonging to the readamplifier block LVB, such as the read amplifier LV for example, areconnected via a local SAN line to an SAN driver output A2. The local SANdriver LTN is driven in an n-phase manner via n drive lines SEN and isconnected to reference potential Vss. The read amplifiers LVB, LVB',LVB'' . . . are assigned to bit line blocks TB, TB', TB'' . . . , thebit line block TB comprising a multiplicity of bit line pairs, such asthe bit line pair BL and BLN for example, and the bit line block TB'comprising a multiplicity of bit line pairs, such as the bit line pairBL' and BLN' for example. FIG. 3 shows, to represent a plurality of wordline blocks, a word line block WLB which consists of word lines WLinterconnected by word line pins N. Representing an entire cell field,memory cells Z with a bit line BL and a word line WL and also a memorycell Z' with a bit line BL' and the word line WL are shown.

If a bit line block TB' favorably corresponds to the number of all bitline pairs between two interconnect pins N of a word line WL, then it ispossible in each case for exactly one gap between the read amplifierblocks LVB, LVB', LVB' . . . produced by the interconnect pins N to beused for local SAN drivers LTN, LTN' . . . Interconnect points for theword line pins N are considerably wider than the word line and arearranged in a staggered manner to minimize the word line spacing, whichresults in a sufficient gap between the read amplifier blocks. Insteadof a global SAN line, which is connected to 1024 read amplifiers forexample, in a dynamic semiconductor memory according to the invention,for instance, an arrangement with 16 local SAN drivers LTN, LTN' . . .and 16 local SAN lines 2, 2' . . . , which are connected in each case to64 read amplifiers LV, is used. In this example, the line resistances ofthe local SAN line are reduced in relation to a global SAN line by afactor of 16, and are thus largely negligible in relation to theinternal resistance of the respective local SAN driver. As a result ofthe substantially lower line resistances of the local SAN lines, acurrent-dependent negative voltage feedback is also negligible, and allread amplifiers LV of a read amplifier block receive largely the samedrive voltage at their SAP inputs E2. This is a prerequisite for the useof an SAN driver with optimized drive function.

If the word lines WL are, for instance, laid in only one plane of alow-resistance material, that is to say no interconnect pins N are used,then the word lines must be shorter and additional word line drivers arenecessary. The gaps formed by the additional word line drivers betweenread amplifier blocks may be advantageously used for local SAN or SAPdrivers.

FIG. 4 represents a detailed circuit of an n-phase local SAN driver of adynamic semiconductor memory according to the invention. The local SANdriver circuit has a minimum of three and a maximum of n n-channeltransistors, which can be driven in the case of the minimum by threedrive lines SEN1 to SEN3, and in the case of the maximum via n drivelines SEN1 to SENn. The drain terminal of an n-channel transistor NT₁ isconnected to an SAN driver output A2, the source terminal is connectedvia a forward-biased diode D₁ to reference potential V_(SS), and thegate of the n-channel transistor NT₁ is connected to the drive lineSEN1. A further n-channel transistor NT₂ is connected in parallel withthe diode D₁ and is connected to a drive line SEN2. Located between theSAN driver output A2 and the reference potential V_(SS) is a thirdn-channel transistor NT₃, which can be driven by a third drive lineSEN3. For better approximation of an optimum drive function, furthern-channel transistors up to a transistor NT_(n), the gate of which isconnected to a drive line SENn, can be connected in parallel with thetransistor NT₃. It is of less importance here whether the drive linesSEN1 . . . SENn can be formed outside the local SAN driver or whetherthey can be formed in the local SAN drivers from, for example, thesignal of the drive line SEN1, by delay circuits in each case.

The diode D₁ is a bipolar diode realized with CMOS process steps, whichis also used at other points of a dynamic semiconductor memory accordingto the invention, and must be dimensioned with respect to its currentstrength in such a way that the junction capacitors connected to the SANline and the line capacitor can be discharged within a reasonable time.By dimensioning the individual transistors and selecting the time ofdriving, the control voltage can be shaped bit by bit, first of all flatand then dropping sharply.

The bit-by-bit formation of an optimized drive function by the localn-phase SAN drivers shown in FIG. 4 is represented in the voltage-timediagram of FIG. 5. The voltage-time diagram shows the voltage U₂ at theSAN driver output A2, provided that the latter is connected via a localSAN line to read amplifiers. If all drive lines SEN1 . . . SENn are atlow potential, then the voltage U₂ corresponds to the precharge levelU_(m), but as soon as the transistor NT₁ becomes conductive in a firstphase B1, the output voltage U₂ drops to a value U_(m) -U_(T) reduced bythe threshold voltage U_(T) of an n-channel read approximately to thethreshold voltage of the diode D1. The actual evaluation begins with thesecond phase B2 in which the channel resistor of the transistor NT₁ isconnected in series with the transistor NT₂. As a result of the furtherconnection of the transistors NT₃ to NT_(n), the internal resistance ofthe SAN driver is specifically reduced step-by-step, which causes theoutput voltage U₂ to drop to the reference potential in accordance withan optimized drive function.

The representation of FIG. 6 shows an arrangement of local SAN and SAPdrivers in blocks in a dynamic semiconductor memory according to theinvention. In a similar manner to FIG. 4, FIG. 6 represents readamplifier blocks LVB, LVB', LVB'' . . . with their associated bit lineblocks TB, TB', TB'' . . . A word line block WLB likewise consists ofword lines WL interconnected with word line pins N, which is connected,in a manner representing all memory cells of a word line block, to amemory cell Z and a memory cell Z'. The read amplifier block LVBconsists of a multiplicity of read amplifiers, such as the readamplifier LV for example, which are connected to bit line pairs, such asthe bit line pair BL and BLN for example. The read amplifier LV comparesthe bit line BL, which is connected to the memory cell Z, with the bitline BLN. And in an analogous manner, the bit line BL', which isconnected to the cell Z', is compared with the bit line BLN' in the readamplifier block LVB'. The essential difference to FIG. 4 are the localp-phase SAP drivers LTP which are present in addition to the localn-phase SAN drivers and can be driven in each case by p-drive lines SEP.The SAN input E2 of a read amplifier LV of a read amplifier block LVB isconnected via a local SAN line 2 to the SAN output A2 of the local SANdriver LTN. In a similar manner, the SAP input E1 of a read amplifier LVof a read amplifier block LVB is connected via a local SAP line 1 to anSAP output A1 of the local SAP driver LTP. This applies analogously tofurther read amplifier blocks, such as the read amplifier block LVB' forexample, which is connected via the local SAP driver line 1' and thelocal SAN driver line 2' to the local SAP driver LTP' and to the localSAN driver LTN'.

In a manner similar to the local SAN drivers, the local SAP drivers LTP,LTP' . . . make it possible to achieve an optimized drive function forthe p-channel parts of the read amplifiers. Owing to the lower majoritycarrier mobility of the p-channel driver transistors, local SAP driverstake up approximately three times as much space as corresponding localSAN drivers. The detailed circuit shown in FIG. 7 of an n-phase localSAP driver in a dynamic semiconductor memory according to the inventionhas a similar structure to the local SAN driver represented in FIG. 4.The local SAP driver has a p-channel transistor PT₁, the drain terminalof which is connected to an SAP driver output A1, the source terminal ofwhich is connected via a forward-biased diode D₂ to the supply voltageV_(DD), and the gate of which is connected to a control line SEP1. Ap-channel transistor PT₂ is connected in parallel with the diode D₂ andthe gate of the transistor PT₂ is connected to a drive line SEP2.Located between the SAP driver output A1 and the supply voltage V_(DD)is a p-channel transistor PT₃, the gate of which can be driven via adrive line SEP3. For better approximation of an optimum drive function,further p-channel transistors up to a transistor PT_(p), the gate ofwhich is connected to the drive line SEP_(p), can be connected inparallel with the transistor PT₃. In a similar way as for the SANdriver, described in FIG. 4, the signals for the further drive linesSEP2 . . . SEPn can also be formed for the SAP driver from, for example,the signal of the drive line SEP1 by delay circuits.

In a first phase, in which the drive line SEP1 receives low potential,the transistor PT₁ becomes conductive and the voltage at the SAP driveroutput A1 rises from a precharge voltage U_(m) to a voltage which islower than the supply voltage V_(DD) only by the threshold voltage ofthe diode D₂. If the transistor PT2 becomes conductive in a secondphase, in which the drive line SEP2 receives low potential, then aseries circuit of the channel resistances of the transistors PT₁ and PT₂is produced. In a third to p^(th) phase, the transistors PT₃ to PT_(p)become successively conductive by low potential on the control linesSEP3 to SEP_(p), and hence the internal resistance of the SAP driver isreduced step by step, the voltage at the SAP driver output A1 beingbrought to the supply voltage V_(DD) in accordance with an optimizeddrive function.

A combination of MOS transistors and bipolar transistors is conceivableboth for the SAN driver and for the SAP driver. The MOS transistorscannot be completely replaced by bipolar transistors since, due to thethreshold voltages occurring with bipolar transistors, a reduction toV_(SS) or a rise to V_(DD) is not possible.

The invention is not limited to the particular details of the apparatusdepicted and other modifications and applications are contemplated.Certain other changes may be made in the above described apparatuswithout departing from the true spirit and scope of the invention hereininvolved. It is intended, therefore, that the subject matter in theabove depiction shall be interpreted as illustrative and not in alimiting sense.

What is claimed is:
 1. A dynamic semiconductor memory, comprising:amemory cell array which has at least one block of memory cells connectedto a group of word lines; read amplifiers, each having an n-channel partand a p-channel part; at least one SAN driver per block of memory cellsconnected to a group of word lines for driving the n-channel parts ofthe read amplifiers; at least one SAP driver per block of memory cellsconnected to a group of word lines for driving the p-channel parts ofthe read amplifiers; at least one block of memory cells connected to agroup of word lines which is subdivided into a plurality of memoryblocks, each memory block connected to a group of bit lines, said memoryblocks connected to a group of bit lines in turn having a plurality ofbit line pairs; said word lines having an electrical contact withsuperimposed conductor tracks which are of low impedance relative to theword lines via word line pins, the bit line pairs respectively locatedbetween two respective word line pins of a word line forming a memoryblock connected to a group of bit lines; a single SAN driver for eachmemory block connected to a respective group of bit lines, forming alocal SAN driver and being driven such that a voltage at its outputdecreases in a piecemeal manner, with different gradients, to enable afast and at the same time reliable reading; and one local SAN driverdriving the n-channel parts of all read amplifiers belonging to a memoryblock via a local SAN line.
 2. The dynamic semiconductor memory asclaimed in claim 1, wherein a local SAN driver belonging to a firstmemory block connected to a first group of bit lines is arrangedspatially on a semiconductor chip such that said local SAN driver islocated between an array of read amplifiers belonging to the firstmemory block and an array of read amplifiers which belong to a furthermemory block connected to a further group of bit lines and directlyadjacent to the first memory block.
 3. The dynamic semiconductor memoryas claimed in claim 1, wherein each of the local SAN drivers contains adiode, which is connected to a reference potential on a cathode sidethereof and is connected to a first terminal of a first n-channeltransistor on an anode side thereof, wherein a second terminal of thefirst n-channel transistor is connected to a driver output of theassociated local SAN driver and a gate terminal of the first n-channeltransistor is driven by a first control signal, wherein a secondn-channel transistor is connected in parallel with the diode and has agate terminal that is driven by a second control signal, and wherein afirst terminal of a third n-channel transistor is connected to thedriver output of the associated local SAN driver, and wherein a secondterminal of the third n-channel transistor is connected to the referencepotential, and a gate terminal of the third n-channel transistor isdriven by a third control signal.
 4. The dynamic semiconductor memory asclaimed in claim 3, wherein at least one further n-channel transistor isconnected in parallel with the third n-channel transistor, a firstterminal of the further n-channel transistor being connected to thedriver output of the associated local SAN driver, and a second terminalof the further n-channel transistor being connected to the referencepotential, and wherein a gate terminal of the further n-channeltransistor is driven by a further control signal.
 5. The dynamicsemiconductor memory as claimed in claim 3, wherein n-channeltransistors of the local SAN drivers have different channel widths. 6.The dynamic semiconductor memory as claimed in claim 1, wherein inaddition to a local SAN driver, a respective SAP driver with optimizeddrive function is connected to each respective memory block and forms alocal SAP driver, and wherein one local SAP driver drives the p-channelparts of all read amplifiers belonging to a respective memory block viaa local SAP line.
 7. The dynamic semiconductor memory as claimed inclaim 6, wherein a local SAP driver belonging to a first memory blockconnected to a first group of bit lines is arranged spatially on asemiconductor chip such that said local SAP driver is located between anarray of read amplifiers belonging to the first memory block and anarray of read amplifiers which belong to a further memory blockconnected to a further group of bit lines and directly adjacent to thefirst memory block.
 8. The dynamic semiconductor memory as claimed inclaim 6, wherein each of the local SAP drivers contains a diode, whichis connected to a supply voltage on an anode side thereof and isconnected to a first terminal of a first p-channel transistor on acathode side thereof, wherein a second terminal of the first p-channeltransistor is connected to a driver output of the associated local SAPdriver and a gate terminal of the first p-channel transistor is drivenby a first control signal, wherein a second p-channel transistor isconnected in parallel with the diode and has a gate terminal that isdriven by a second control signal, and wherein a first terminal of athird p-channel transistor is connected to the driver output of theassociated local SAP driver, and a second terminal of the thirdp-channel transistor is connected to the supply voltage, and a gateterminal of the third p-channel transistor is driven by a third controlsignal.
 9. The dynamic semiconductor memory as claimed in claim 8,wherein at least one further p-channel transistor is connected inparallel with the third p-channel transistor, a first terminal of thefurther p-channel transistor being connected to the driver output of thelocal SAP driver, and a second terminal of the further p-channeltransistor being connected to the supply voltage, and wherein a gateterminal of the further p-channel transistor is driven by a furthercontrol signal.
 10. The dynamic semiconductor memory as claimed in claim8, wherein p-channel transistors of the local SAP drivers have differentchannel widths.
 11. The dynamic semiconductor memory as claimed in claim4, wherein n-channel transistors of the local SAN drivers have differentchannel widths.
 12. The dynamic semiconductor memory as claimed in claim9, wherein p-channel transistors of the local SAP drivers have differentchannel widths.
 13. A dynamic semiconductor memory, comprising:a memorycell array which has at least one block of memory cells connected to agroup of word lines; read amplifiers, each having an n-channel part anda p-channel part; at least one SAN driver per block of memory cellsconnected to a group of word lines for driving the n-channel parts ofthe read amplifiers; at least one SAP driver per block of memory cellsconnected to a group of word lines for driving the p-channel parts ofthe read amplifiers; at least one block of memory cells connected to agroup of word lines which is subdivided into a plurality of memoryblocks, each memory block connected to a group of bit lines, said memoryblocks connected to a group of bit lines in turn having a plurality ofbit lines pairs; said word lines being only in a plane of low-impedancematerial with additional word line drivers, the bit line pairsrespectively located between two respective word line drivers of a wordline forming a memory block connected to a group of bit lines; a singleSAN driver for each memory block, forming a local SAN driver and beingdriven such that a voltage at its output decreases in a piecemealmanner, with different gradients, to enable a fast and at the same timereliable reading; and one local SAN driver driving the n-channel partsof all read amplifiers belonging to a memory block via a local SAN line.14. The dynamic semiconductor memory as claimed in claim 13, wherein alocal SAN driver belonging to a first memory block connected to a firstgroup of bit lines is arranged spatially on a semiconductor chip suchthat said local SAN driver is located between an array of readamplifiers belonging to the first memory block and an array of readamplifiers which belong to a further memory block connected to a furthergroup of bit lines and directly adjacent to the first memory block. 15.The dynamic semiconductor memory as claimed in claim 13, wherein each ofthe local SAN drivers contains a diode, which is connected to areference potential on a cathode side thereof and is connected to afirst terminal of a first n-channel transistor on an anode side thereof,wherein a second terminal of the first n-channel transistor is connectedto a driver output of the associated local SAN driver and a gateterminal of the first n-channel transistor is driven by a first controlsignal, wherein a second n-channel transistor is connected in parallelwith the diode and has a gate terminal that is driven by a secondcontrol signal, and wherein a first terminal of a third n-channeltransistor is connected to the driver output of the associated local SANdriver, and wherein a second terminal of the third n-channel transistoris connected to the reference potential, and a gate terminal of thethird n-channel transistor is driven by a third control signal.
 16. Thedynamic semiconductor memory as claimed in claim 15, wherein at leastone further n-channel transistor is connected in parallel with the thirdn-channel transistor, a first terminal of the further n-channeltransistor being connected to the driver output of the associated localSAN driver, and a second terminal of the further n-channel transistorbeing connected to the reference potential, and wherein a gate terminalof the further n-channel transistor is driven by a further controlsignal.
 17. The dynamic semiconductor memory as claimed in claim 15,wherein n-channel transistors of the local SAN drivers have differentchannel widths.
 18. The dynamic semiconductor memory as claimed in claim13, wherein, in addition to a local SAN driver, a respective SAP driverwith optimized drive function is connected to each respective memoryblock and forms a local SAP driver, and wherein one local SAP driverdrives the p-channel parts of all read amplifiers belonging to arespective memory block via a local SAP line.
 19. The dynamicsemiconductor memory as claimed in claim 18, wherein a local SAP driverbelonging to a first memory block connected to a first group of bitlines is arranged spatially on a semiconductor chip such that said localSAP driver is located between an array of read amplifiers belonging tothe first memory block and an array of read amplifiers belong to afurther memory block connected to a further group of bit lines anddirectly adjacent to the first memory block.
 20. The dynamicsemiconductor memory as claimed in claim 18, wherein each of the localSAP drivers contains a diode, which is connected to a supply voltage onan anode side thereof and is connected to a first terminal of a firstp-channel transistor on a cathode side thereof, wherein a secondterminal of the first p-channel transistor is connected to a driveroutput of the associated local SAP driver and a gate terminal of thefirst p-channel transistor is driven by a first control signal, whereina second p-channel transistor is connected in parallel with the diodeand has a gate terminal that is driven by a second control signal, andwherein a first terminal of a third p-channel transistor is connected tothe driver output of the associated local SAP driver, and a secondterminal of the third p-channel transistor is connected to the supplyvoltage, and a gate terminal of the third p-channel transistor is drivenby a third control signal.
 21. The dynamic semiconductor memory asclaimed in claim 20, wherein at least one further p-channel transistoris connected in parallel with the third p-channel transistor, a firstterminal of the further p-channel transistor being connected to thedriver output of the local SAP driver, and a second terminal of thefurther p-channel transistor being connected to the supply voltage, andwherein a gate terminal of the further p-channel transistor is driven bya further control signal.
 22. The dynamic semiconductor memory asclaimed in claim 20, wherein p-channel transistors of the local SAPdrivers have different channel widths.
 23. The dynamic semiconductormemory as claimed in claim 16, wherein n-channel transistors of thelocal SAN drivers have different channel widths.
 24. The dynamicsemiconductor memory as claimed in claim 21, wherein p-channeltransistors of the local SAP drivers have different channel widths. 25.A dynamic semiconductor memory, comprising:a memory cell array which hasat least one block of memory cells connected to a group of word lines;read amplifiers, each having an n-channel part and a p-channel part; atleast one SAN driver per block of memory cells connected to a group ofword lines for driving the n-channel parts of the read amplifiers; atleast one SAP driver per block of memory cells connected to a group ofword lines for driving the p-channel parts of the read amplifiers; atleast one block of memory cells connected to a group of word lines whichis subdivided into a plurality of memory blocks, each memory blockconnected to a group of bit lines, said memory blocks connected to agroup of bit lines in turn having a plurality of bit lines pairs; saidword lines being only in a plane of low-impedance material withadditional word line drivers, the bit line pairs respectively locatedbetween two respective word line drivers of a word line forming a memoryblock connected to a group of bit lines; a single SAN driver for eachmemory block, forming a local SAN driver and being driven such that avoltage at its output decreases in a piecemeal manner with differentgradients, to enable a fast and at the same time reliable reading; onelocal SAN driver driving the n-channel parts of all read amplifiersbelonging to a memory block via a local SAN line; and each of the localSAN drivers having a diode, which is connected to a reference potentialon a cathode side thereof and is connected to a first terminal of afirst n-channel transistor on an anode side thereof, a second terminalof the first n-channel transistor connected to a driver output of theassociated local SAN driver and a gate terminal of the first n-channeltransistor driven by a first control signal, a second n-channeltransistor connected in parallel with the diode and having a gateterminal that is driven by a second control signal, a first terminal ofa third n-channel transistor connected to the driver output of theassociated local SAN driver, and a second terminal of the thirdn-channel transistor connected to the reference potential, and a gateterminal of the third n-channel transistor driven by a third controlsignal.
 26. The dynamic semiconductor memory as claimed in claim 25,wherein at least one further n-channel transistor is connected inparallel with the third n-channel transistor, a first terminal of thefurther n-channel transistor being connected to the driver output of theassociated local SAN driver, and a second terminal of the furthern-channel transistor being connected to the reference potential, andwherein a gate terminal of the further n-channel transistor is driven bya fruther control signal.
 27. The dynamic semiconductor memory asclaimed in claim 25, wherein n-channel transistors of the local SANdrivers have different channel widths.
 28. The dynamic semiconductormemory as claimed in claim 25, wherein, in addition to a local SANdriver, a respective SAP driver with optimized drive function isconnected to each respective memory block and forms a local SAP driver,wherein one local SAP driver drives the p-channel parts of all readamplifiers belonging to a respective memory block via a local SAP line;and wherein each of the local SAP drivers contains a diode, which isconnected to a supply voltage on an anode side thereof and is connectedto a first terminal of a first p-channel transistor on a cathode sidethereof, a second terminal of the first p-channel transistor beingconnected to a driver output of the associated local SAP driver and agate terminal of the first p-channel transistor driven by a firstcontrol signal, a second p-channel transistor being connected inparallel with the diode and having a gate terminal that is driven by asecond control signal, a first terminal of a third p-channel transistorbeing connected to the driver output of the associated local SAP driver,and a second terminal of the third p-channel transistor being connectedto the supply voltage, and a gate terminal of the third p-channeltransistor being driven by a third control signal.
 29. The dynamicsemiconductor memory as claimed in claim 28, wherein at least onefurther p-channel transistor is connected in parallel with the thirdp-channel transistor, a first terminal of the further p-channeltransistor being connected to the driver output of the local SAP driver,and a second terminal of the further p-channel transistor beingconnected to the supply voltage, and wherein a gate terminal of thefurther p-channel transistor is driven by a further control signal. 30.The dynamic semiconductor memory as claimed in claim 28, whereinp-channel transistors of the local SAP drivers have different channelwidths.
 31. The dynamic semiconductor memory as claimed in claim 26,wherein n-channel transistors of the local SAN drivers have differentchannel widths.
 32. The dynamic semiconductor memory as claimed in claim29, wherein p-channel transistors of the local SAP drivers havedifferent channel widths.
 33. A dynamic semiconductor memory,comprising:a memory cell array which has at least one block of memorycells connected to a group of word lines; read amplifiers, each havingan n-channel part and a p-channel part; at least one SAN driver perblock of memory cells connected to a group of word lines for driving then-channel parts of the read amplifiers; at least one SAP driver perblock of memory cells connected to a group of word lines for driving thep-channel parts of the read amplifiers; at least one block of memorycells connected to a group of word lines which is subdivided into aplurality of memory blocks, each memory block connected to a group ofbit lines, said memory blocks connected to a group of bit lines in turnhaving a plurality of bit lines pairs; said word lines having anelectrical contact with superimposed conductor tracts which are of lowimpedance relative to the word lines via word line pins, the bit linepairs respectively located between two respective word line pins of aword line forming a memory block; a single SAN driver for each memoryblock connected to a respective group of bit lines, forming a local SANdriver and being driven such that a voltage at its output decreases in apiecemeal manner, with different gradients, to enable a fast and at thesame time reliable reading; one local SAN driver driving the n-channelparts of all read amplifiers belonging to a memory block via a local SANline; and each of the local SAN drivers having a diode, which isconnected to a reference potential on a cathode side thereof and isconnected to a first terminal of a first n-channel transistor on ananode side thereof, a second terminal of the first n-channel transistorconnected to a driver output of the associated local SAN driver and agate terminal of the first n-channel transistor driven by a firstcontrol signal, a second n-channel transistor connected in parallel withthe diode and having a gate terminal driven by a second control signal,a first terminal of a third n-channel transistor connected to the driveroutput of the associated local SAN driver, and a second terminal of thethird n-channel transistor connected to the reference potential, and agate terminal of the third n-channel transistor driven by a thirdcontrol signal.
 34. The dynamic semiconductor memory as claimed in claim33, wherein at least one further n-channel transistor is connected inparallel with the third n-channel transistor, a first terminal of thefurther n-channel transistor being connected to the driver output of theassociated local SAN driver, and a second terminal of the furthern-channel transistor being connected to the reference potential, andwherein a gate terminal of the further n-channel transistor is driven bya further control signal.
 35. The dynamic semiconductor memory asclaimed in claim 33, wherein n-channel transistors of the local SANdrivers have different channel widths.
 36. The dynamic semiconductormemory as claimed in claim 33, wherein, in addition to a local SANdriver, a respective SAP driver with optimized drive function isconnected to each respective memory block and forms a local SAP driver,wherein one local SAP driver drives the p-channel parts of all readamplifiers belonging to a respective memory block via a local SAP line;and wherein each of the local SAP drivers contains a diode, which isconnected to a supply voltage on an anode side thereof and is connectedto a first terminal of a first p-channel transistor on a cathode sidethereof, a second terminal of the first p-channel transistor beingconnected to a driver output of the associated local SAP driver and agate terminal of the first p-channel transistor being driven by a firstcontrol signal, a second p-channel transistor being connected inparallel with the diode and having a gate terminal that is driven by asecond control signal, a first terminal of a third p-channel transistorbeing connected to the driver output of the associated local SAP driver,and a second terminal of the third p-channel transistor being connectedto the supply voltage, and a gate terminal of the third p-channeltransistor being driven by a third control signal.
 37. The dynamicsemiconductor memory as claimed in claim 36, wherein at least onefurther p-channel transistor is connected in parallel with the thirdp-channel transistor, a first terminal of the further p-channeltransistor being connected to the driver output of the local SAP driver,and a second terminal of the further p-channel transistor beingconnected to the supply voltage, and wherein a gate terminal of thefurther p-channel transistor is driven by a further control signal. 38.The dynamic semiconductor memory as claimed in claim 36, whereinp-channel transistors of the local SAP drivers have different channelwidths.
 39. The dynamic semiconductor memory as claimed in claim 34,wherein n-channel transistors of the local SAN drivers have differentchannel widths.
 40. The dynamic semiconductor memory as claimed in claim37, wherein p-channel transistors of the local SAP drivers havedifferent channel widths.